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94 caution: these devices are sensitive to electrostatic discharge; follow proper esd handling procedures. ultrafet? is a trademark of intersil corporation. pspice? is a registered trademark of microsim corporation. saber is a copyright of analogy, inc. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 huf75332g3, huf75332p3, HUF75332S3S 60a, 55v, 0.019 ohm, n-channel ultrafet power mosfets these n-channel power mosfets are manufactured using the innovative ultrafet? process. this advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. this device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. it was designed for use in applications where power ef?ciency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low- voltage bus switches, and power management in portable and battery-operated products. formerly developmental type ta75332. features ? 60a, 55v ? simulation models - temperature compensated pspice ? and saber ? models - spice and saber thermal impedance models available on the web at: www.intersil.com ? peak current vs pulse width curve ? uis rating curve ? related literature - tb334, guidelines for soldering surface mount components to pc boards symbol packaging ordering information part number package brand huf75332g3 to-247 75332g huf75332p3 to-220ab 75332p HUF75332S3S to-263ab 75332s note: when ordering, use the entire part number. add the suffix t to obtain the to-263ab variant in tape and reel, e.g., HUF75332S3St. d g s jedec style to-247 jedec to-220ab jedec to-263ab source drain gate drain (tab) drain source gate drain (flange) gate source drain (flange) data sheet june 1999 file number 4489.3
95 absolute maximum ratings t c = 25 o c, unless otherwise specified units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 55 v drain to gate voltage (r gs = 20k w ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 55 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v drain current continuous (figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 60 figure 4 a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as figures 6, 14, 15 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 0.97 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?cations t c = 25 o c, unless otherwise speci?ed parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 m a, v gs = 0v (figure 11) 55 - - v zero gate voltage drain current i dss v ds = 50v, v gs = 0v - - 1 m a v ds = 45v, v gs = 0v, t c = 150 o c - - 250 m a gate to source leakage current i gss v gs = 20v - - 100 na on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 m a (figure 10) 2 - 4 v drain to source on resistance r ds(on) i d = 60a, v gs = 10v (figure 9) - 0.016 0.019 w thermal specifications thermal resistance junction to case r q jc (figure 3) - - 1.03 o c/w thermal resistance junction to ambient r q ja to-247 - - 30 o c/w to-220, to-263 - - 62 o c/w switching specifications (v gs = 10v) turn-on time t on v dd = 30v, i d @ 60a, r l = 0.50 w , v gs = 10v, r gs = 6.8 w - - 100 ns turn-on delay time t d(on) -12- ns rise time t r -55- ns turn-off delay time t d(off) -11- ns fall time t f -25- ns turn-off time t off - - 55 ns gate charge specifications total gate charge q g(tot) v gs = 0v to 20v v dd = 30v, i d @ 60a, r l = 0.50 w i g(ref) = 1.0ma (figure 13) -7085nc gate charge at 10v q g(10) v gs = 0v to 10v - 40 50 nc threshold gate charge q g(th) v gs = 0v to 2v - 2.5 3.0 nc gate to source gate charge q gs -6-nc reverse transfer capacitance q gd -15- nc huf75332g3, huf75332p3, HUF75332S3S
96 capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 12) - 1300 - pf output capacitance c oss - 480 - pf reverse transfer capacitance c rss - 115 - pf electrical speci?cations t c = 25 o c, unless otherwise speci?ed parameter symbol test conditions min typ max units source to drain diode speci?cations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 60a - - 1.25 v reverse recovery time t rr i sd = 60a, di sd /dt = 100a/ m s--75ns reverse recovered charge q rr i sd = 60a, di sd /dt = 100a/ m s - - 140 nc typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 175 i d , drain current (a) t c , case temperature ( o c) 20 40 60 80 50 75 100 125 150 175 0 25 t, rectangular pulse duration (s) single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z q jc x r q jc + t c p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -5 0.1 1 2 0.01 z q jc , normalized thermal impedance huf75332g3, huf75332p3, HUF75332S3S
97 figure 4. peak current capability figure 5. forward bias safe operating area note: refer to intersil application notes an9321 and an9322. figure 6. unclamped inductive switching capability figure 7. saturation characteristics figure 8. transfer characteristics typical performance curves (continued) 10 1 10 0 10 -1 10 -2 10 -3 10 -4 10 -5 50 100 1000 t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: v gs = 10v i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region 10 100 500 10 100 1 1 200 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t c = 25 o c 100 m s 10ms 1ms v dss(max) = 55v limited by r ds(on) area may be operation in this starting tj = 25oc 10 100 0.001 0.01 0.1 1 10 500 t av , time in avalanche (ms) i as , avalanche current (a) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 1 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 0 30 60 90 120 150 0 1.5 3.0 4.5 6.0 7.5 v ds , drain to source voltage (v) pulse duration = 80 m s t c = 25 o c i d , drain current (a) v gs = 5v v gs = 6v v gs = 10v v gs = 7v v gs = 20v duty cycle = 0.5% max 0 30 60 90 120 150 0 1.5 3.0 4.5 6.0 7.5 v gs , gate to source voltage (v) v dd = 15v 175 o c -55 o c 25 o c i d , drain current (a) pulse duration = 80 m s duty cycle = 0.5% max huf75332g3, huf75332p3, HUF75332S3S
98 figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature figure 11. normalized drain to source breakdown voltage vs junction temperature figure 12. capacitance vs drain to source voltage note: refer to intersil application notes an7254 and an7260. figure 13. gate charge waveforms for constant gate current typical performance curves (continued) 1.0 1.5 2.0 2.5 -40 0 40 80 120 160 200 0.5 -80 normalized drain to source t j , junction temperature ( o c) on resistance pulse duration = 80 m s v gs = 10v, i d = 60a duty cycle = 0.5% max 0.8 1.0 1.2 -40 0 40 80 120 160 200 0.6 -80 normalized gate t j , junction temperature ( o c) threshold voltage v gs = v ds , i d = 250 m a 1.0 1.1 1.2 -40 0 40 80 120 160 200 0.9 -80 t j , junction temperature ( o c) normalized drain to source i d = 250 m a breakdown voltage 0 500 1000 1500 2000 0 102030405060 v ds , drain to source voltage (v) c, capacitance (pf) c iss c oss c rss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss ? c ds + c gd 2 4 6 8 10 10 20 30 40 50 60 0 0 v gs , gate to source voltage (v) v dd = 30v q g , gate charge (nc) i d = 60a i d = 45a i d = 30a i d = 15a waveforms in descending order: huf75332g3, huf75332p3, HUF75332S3S
99 test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms figure 16. gate charge test circuit figure 17. gate charge waveform figure 18. switching time test circuit figure 19. resistive switching waveforms t p v gs 0.01 w l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 huf75332g3, huf75332p3, HUF75332S3S
100 pspice electrical model .subckt huf75332 2 1 3 ; rev 17 february 1999 ca 12 8 1.8e-9 cb 15 14 1.73e-9 cin 6 8 1.19e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 58.85 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 1e-9 lsource 3 7 1e-9 k1 lsource lgate 0.0085 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 4.5e-3 rgate 9 20 1.3 rldrain 2 5 10 rlgate 1 9 10 rlsource 3 7 10 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 5.95e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*180),4.6))} .model dbodymod d (is = 1.3e-12 rs = 3.0e-3 ikf = 20 xti = 6 trs1 = 2.7e-3 trs2 = 7.0e-7 cjo = 1.7e-9 tt = 4.0e-8 m = 0.45 vj = 0.75 ) .model dbreakmod d (rs = 1.71e-2 ikf = 1.0e-5 trs1 = -4.0e-4 trs2 = -1.55e-5) .model dplcapmod d (cjo = 1.8e-9 is = 1e-30 n = 1 m = 0.9 vj = 1.45) .model mmedmod nmos (vto = 3.183 kp = 2 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 1.3) .model mstromod nmos (vto = 3.66 kp = 51.5 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 2.703 kp = 0.008 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 13) .model rbreakmod res (tc1 = 1.05e-3 tc2 = 4.5e-7) .model rdrainmod res (tc1 = 1.16e-2 tc2 = 1.7e-5) .model rslcmod res (tc1 = 3.96e-3 tc2 = 2.7e-6) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-5) .model rvthresmod res (tc1 = -2.8e-3 tc2 = -1.0e-5) .model rvtempmod res (tc1 = -2.75e-3 tc2 = 5.0e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -8 voff= -3) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -3 voff= -8) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 0 voff= 0.5) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.5 voff= 0) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf75332g3, huf75332p3, HUF75332S3S
101 saber electrical model rev 17 february 1999 template huf75332 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 1.3e-12, xti = 6, cjo = 1.7e-9, tt = 4.0e-8, m = 0.45, vj = 0.75) d..model dbreakmod = () d..model dplcapmod = (cjo = 1.8e-9, is = 1e-30, m = 0.9, vj = 1.45) m..model mmedmod = (type=_n, vto = 3.183, kp = 2, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.66, kp = 51.5, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.703, kp = 8.0e-3, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8, voff = -3) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -8) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0) c.ca n12 n8 = 1.8e-9 c.cb n15 n14 = 1.73e-9 c.cin n6 n8 = 1.19e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 1.0e-9 l.lsource n3 n7 = 1.0e-9 k.kl i (l.lgate) i (l.lsource) = l (l.lgate), l (l.lsource), 0.0085 m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 4.5e-7 res.rdbody n71 n5 = 3.0e-3, tc1 = 2.7e-3, tc2 = 7.0e-7 res.rdbreak n72 n5 = 1.71e-2, tc1 = -4.0e-4, tc2 = -1.55e-5 res.rdrain n50 n16 = 4.5e-3, tc1 = 1.16e-2, tc2 = 1.7e-5 res.rgate n9 n20 = 1.3 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10 res.rlsource n3 n7 = 10 res.rslc1 n5 n51 = 1e-6, tc1 = 3.96e-3, tc2 = 2.7e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.95e-3, tc1 = 1e-3, tc2 = 1e-5 res.rvtemp n18 n19 = 1, tc1 = -2.75e-3, tc2 = 5.0e-7 res.rvthres n22 n8 = 1, tc1 = -2.8e-3, tc2 = -1.0e-5 spe.ebreak n11 n7 n17 n18 = 58.85 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 4.6)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbody rdbreak 72 71 huf75332g3, huf75332p3, HUF75332S3S
102 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com spice thermal model rev 11february 1999 huf75332 ctherm1 th 6 4.00e-3 ctherm2 6 5 7.00e-3 ctherm3 5 4 7.50e-3 ctherm4 4 3 8.00e-3 ctherm5 3 2 1.85e-2 ctherm6 2 tl 12.55 rtherm1 th 6 7.09e-3 rtherm2 6 5 1.77e-2 rtherm3 5 4 4.97e-2 rtherm4 4 3 2.79e-1 rtherm5 3 2 4.21e-1 rtherm6 2 tl 5.58e-2 saber thermal model saber thermal model huf75332 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 4.00e-3 ctherm.ctherm2 6 5 = 7.00e-3 ctherm.ctherm3 5 4 = 7.50e-3 ctherm.ctherm4 4 3 = 8.00e-3 ctherm.ctherm5 3 2 = 1.85e-2 ctherm.ctherm6 2 tl = 12.55 rtherm.rtherm1 th 6 = 7.09e-3 rtherm.rtherm2 6 5 = 1.77e-2 rtherm.rtherm3 5 4 = 4.97e-2 rtherm.rtherm4 4 3 = 2.79e-1 rtherm.rtherm5 3 2 = 4.21e-1 rtherm.rtherm6 2 tl = 5.58e-2 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case huf75332g3, huf75332p3, HUF75332S3S
94 caution: these devices are sensitive to electrostatic discharge; follow proper esd handling procedures. ultrafet? is a trademark of intersil corporation. pspice? is a registered trademark of microsim corporation. saber is a copyright of analogy, inc. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 huf75332g3, huf75332p3, HUF75332S3S 60a, 55v, 0.019 ohm, n-channel ultrafet power mosfets these n-channel power mosfets are manufactured using the innovative ultrafet? process. this advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. this device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. it was designed for use in applications where power ef?ciency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low- voltage bus switches, and power management in portable and battery-operated products. formerly developmental type ta75332. features ? 60a, 55v ? simulation models - temperature compensated pspice ? and saber ? models - spice and saber thermal impedance models available on the web at: www.intersil.com ? peak current vs pulse width curve ? uis rating curve ? related literature - tb334, guidelines for soldering surface mount components to pc boards symbol packaging ordering information part number package brand huf75332g3 to-247 75332g huf75332p3 to-220ab 75332p HUF75332S3S to-263ab 75332s note: when ordering, use the entire part number. add the suffix t to obtain the to-263ab variant in tape and reel, e.g., HUF75332S3St. d g s jedec style to-247 jedec to-220ab jedec to-263ab source drain gate drain (tab) drain source gate drain (flange) gate source drain (flange) data sheet june 1999 file number 4489.3
95 absolute maximum ratings t c = 25 o c, unless otherwise specified units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 55 v drain to gate voltage (r gs = 20k w ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 55 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v drain current continuous (figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 60 figure 4 a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as figures 6, 14, 15 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 0.97 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio nofthe device at these or any other conditions above those indicated in the operational sections of this speci?cation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?cations t c = 25 o c, unless otherwise speci?ed parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 m a, v gs = 0v (figure 11) 55 - - v zero gate voltage drain current i dss v ds = 50v, v gs = 0v - - 1 m a v ds = 45v, v gs = 0v, t c = 150 o c - - 250 m a gate to source leakage current i gss v gs = 20v - - 100 na on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 m a (figure 10) 2 - 4 v drain to source on resistance r ds(on) i d = 60a, v gs = 10v (figure 9) - 0.016 0.019 w thermal specifications thermal resistance junction to case r q jc (figure 3) - - 1.03 o c/w thermal resistance junction to ambient r q ja to-247 - - 30 o c/w to-220, to-263 - - 62 o c/w switching specifications (v gs = 10v) turn-on time t on v dd = 30v, i d @ 60a, r l = 0.50 w , v gs = 10v, r gs = 6.8 w - - 100 ns turn-on delay time t d(on) -12- ns rise time t r -55- ns turn-off delay time t d(off) -11- ns fall time t f -25- ns turn-off time t off - - 55 ns gate charge specifications total gate charge q g(tot) v gs = 0v to 20v v dd = 30v, i d @ 60a, r l = 0.50 w i g(ref) = 1.0ma (figure 13) -7085nc gate charge at 10v q g(10) v gs = 0v to 10v - 40 50 nc threshold gate charge q g(th) v gs = 0v to 2v - 2.5 3.0 nc gate to source gate charge q gs -6-nc reverse transfer capacitance q gd -15- nc huf75332g3, huf75332p3, HUF75332S3S
96 capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 12) - 1300 - pf output capacitance c oss - 480 - pf reverse transfer capacitance c rss - 115 - pf electrical speci?cations t c = 25 o c, unless otherwise speci?ed parameter symbol test conditions min typ max units source to drain diode speci?cations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 60a - - 1.25 v reverse recovery time t rr i sd = 60a, di sd /dt = 100a/ m s--75ns reverse recovered charge q rr i sd = 60a, di sd /dt = 100a/ m s - - 140 nc typical performance curves figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance t c , case temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 175 i d , drain current (a) t c , case temperature ( o c) 20 40 60 80 50 75 100 125 150 175 0 25 t, rectangular pulse duration (s) single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z q jc x r q jc + t c p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -5 0.1 1 2 0.01 z q jc , normalized thermal impedance huf75332g3, huf75332p3, HUF75332S3S
97 figure 4. peak current capability figure 5. forward bias safe operating area note: refer to intersil application notes an9321 and an9322. figure 6. unclamped inductive switching capability figure 7. saturation characteristics figure 8. transfer characteristics typical performance curves (continued) 10 1 10 0 10 -1 10 -2 10 -3 10 -4 10 -5 50 100 1000 t c = 25 o c i = i 25 175 - t c 150 for temperatures above 25 o c derate peak current as follows: v gs = 10v i dm , peak current (a) t, pulse width (s) transconductance may limit current in this region 10 100 500 10 100 1 1 200 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t c = 25 o c 100 m s 10ms 1ms v dss(max) = 55v limited by r ds(on) area may be operation in this starting tj = 25oc 10 100 0.001 0.01 0.1 1 10 500 t av , time in avalanche (ms) i as , avalanche current (a) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 1 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] 0 30 60 90 120 150 0 1.5 3.0 4.5 6.0 7.5 v ds , drain to source voltage (v) pulse duration = 80 m s t c = 25 o c i d , drain current (a) v gs = 5v v gs = 6v v gs = 10v v gs = 7v v gs = 20v duty cycle = 0.5% max 0 30 60 90 120 150 0 1.5 3.0 4.5 6.0 7.5 v gs , gate to source voltage (v) v dd = 15v 175 o c -55 o c 25 o c i d , drain current (a) pulse duration = 80 m s duty cycle = 0.5% max huf75332g3, huf75332p3, HUF75332S3S
98 figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature figure 11. normalized drain to source breakdown voltage vs junction temperature figure 12. capacitance vs drain to source voltage note: refer to intersil application notes an7254 and an7260. figure 13. gate charge waveforms for constant gate current typical performance curves (continued) 1.0 1.5 2.0 2.5 -40 0 40 80 120 160 200 0.5 -80 normalized drain to source t j , junction temperature ( o c) on resistance pulse duration = 80 m s v gs = 10v, i d = 60a duty cycle = 0.5% max 0.8 1.0 1.2 -40 0 40 80 120 160 200 0.6 -80 normalized gate t j , junction temperature ( o c) threshold voltage v gs = v ds , i d = 250 m a 1.0 1.1 1.2 -40 0 40 80 120 160 200 0.9 -80 t j , junction temperature ( o c) normalized drain to source i d = 250 m a breakdown voltage 0 500 1000 1500 2000 0 102030405060 v ds , drain to source voltage (v) c, capacitance (pf) c iss c oss c rss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss ? c ds + c gd 2 4 6 8 10 10 20 30 40 50 60 0 0 v gs , gate to source voltage (v) v dd = 30v q g , gate charge (nc) i d = 60a i d = 45a i d = 30a i d = 15a waveforms in descending order: huf75332g3, huf75332p3, HUF75332S3S
99 test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms figure 16. gate charge test circuit figure 17. gate charge waveform figure 18. switching time test circuit figure 19. resistive switching waveforms t p v gs 0.01 w l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20v v ds v gs i g(ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 huf75332g3, huf75332p3, HUF75332S3S
100 pspice electrical model .subckt huf75332 2 1 3 ; rev 17 february 1999 ca 12 8 1.8e-9 cb 15 14 1.73e-9 cin 6 8 1.19e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 58.85 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 1e-9 lsource 3 7 1e-9 k1 lsource lgate 0.0085 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 4.5e-3 rgate 9 20 1.3 rldrain 2 5 10 rlgate 1 9 10 rlsource 3 7 10 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 5.95e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*180),4.6))} .model dbodymod d (is = 1.3e-12 rs = 3.0e-3 ikf = 20 xti = 6 trs1 = 2.7e-3 trs2 = 7.0e-7 cjo = 1.7e-9 tt = 4.0e-8 m = 0.45 vj = 0.75 ) .model dbreakmod d (rs = 1.71e-2 ikf = 1.0e-5 trs1 = -4.0e-4 trs2 = -1.55e-5) .model dplcapmod d (cjo = 1.8e-9 is = 1e-30 n = 1 m = 0.9 vj = 1.45) .model mmedmod nmos (vto = 3.183 kp = 2 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 1.3) .model mstromod nmos (vto = 3.66 kp = 51.5 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 2.703 kp = 0.008 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 13) .model rbreakmod res (tc1 = 1.05e-3 tc2 = 4.5e-7) .model rdrainmod res (tc1 = 1.16e-2 tc2 = 1.7e-5) .model rslcmod res (tc1 = 3.96e-3 tc2 = 2.7e-6) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-5) .model rvthresmod res (tc1 = -2.8e-3 tc2 = -1.0e-5) .model rvtempmod res (tc1 = -2.75e-3 tc2 = 5.0e-7) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -8 voff= -3) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -3 voff= -8) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = 0 voff= 0.5) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.5 voff= 0) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 huf75332g3, huf75332p3, HUF75332S3S
101 saber electrical model rev 17 february 1999 template huf75332 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 1.3e-12, xti = 6, cjo = 1.7e-9, tt = 4.0e-8, m = 0.45, vj = 0.75) d..model dbreakmod = () d..model dplcapmod = (cjo = 1.8e-9, is = 1e-30, m = 0.9, vj = 1.45) m..model mmedmod = (type=_n, vto = 3.183, kp = 2, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.66, kp = 51.5, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.703, kp = 8.0e-3, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8, voff = -3) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -8) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0) c.ca n12 n8 = 1.8e-9 c.cb n15 n14 = 1.73e-9 c.cin n6 n8 = 1.19e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 1.0e-9 l.lsource n3 n7 = 1.0e-9 k.kl i (l.lgate) i (l.lsource) = l (l.lgate), l (l.lsource), 0.0085 m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = 4.5e-7 res.rdbody n71 n5 = 3.0e-3, tc1 = 2.7e-3, tc2 = 7.0e-7 res.rdbreak n72 n5 = 1.71e-2, tc1 = -4.0e-4, tc2 = -1.55e-5 res.rdrain n50 n16 = 4.5e-3, tc1 = 1.16e-2, tc2 = 1.7e-5 res.rgate n9 n20 = 1.3 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10 res.rlsource n3 n7 = 10 res.rslc1 n5 n51 = 1e-6, tc1 = 3.96e-3, tc2 = 2.7e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.95e-3, tc1 = 1e-3, tc2 = 1e-5 res.rvtemp n18 n19 = 1, tc1 = -2.75e-3, tc2 = 5.0e-7 res.rvthres n22 n8 = 1, tc1 = -2.8e-3, tc2 = -1.0e-5 spe.ebreak n11 n7 n17 n18 = 58.85 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 4.6)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbody rdbreak 72 71 huf75332g3, huf75332p3, HUF75332S3S
102 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com spice thermal model rev 11february 1999 huf75332 ctherm1 th 6 4.00e-3 ctherm2 6 5 7.00e-3 ctherm3 5 4 7.50e-3 ctherm4 4 3 8.00e-3 ctherm5 3 2 1.85e-2 ctherm6 2 tl 12.55 rtherm1 th 6 7.09e-3 rtherm2 6 5 1.77e-2 rtherm3 5 4 4.97e-2 rtherm4 4 3 2.79e-1 rtherm5 3 2 4.21e-1 rtherm6 2 tl 5.58e-2 saber thermal model saber thermal model huf75332 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 4.00e-3 ctherm.ctherm2 6 5 = 7.00e-3 ctherm.ctherm3 5 4 = 7.50e-3 ctherm.ctherm4 4 3 = 8.00e-3 ctherm.ctherm5 3 2 = 1.85e-2 ctherm.ctherm6 2 tl = 12.55 rtherm.rtherm1 th 6 = 7.09e-3 rtherm.rtherm2 6 5 = 1.77e-2 rtherm.rtherm3 5 4 = 4.97e-2 rtherm.rtherm4 4 3 = 2.79e-1 rtherm.rtherm5 3 2 = 4.21e-1 rtherm.rtherm6 2 tl = 5.58e-2 } rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 th junction case huf75332g3, huf75332p3, HUF75332S3S

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